functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a four-channel sample-and-hold amplifier AD684* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features four matched sample-and-hold amplifiers independent inputs, outputs and control pins 500 ns hold mode settling 1 m s maximum acquisition time to 0.01% low droop rate: 0.01 m v/ m s internal hold capacitors 75 ps maximum aperture jitter low power dissipation: 430 mw 0.3" skinny dip package mil-std-883 compliant versions available product highlights 1. fast acquisition time (1 m s) and low aperture jitter (75 ps) make the AD684 the best choice for multiple channel data acquisition systems. 2. monolithic construction insures excellent interchannel matching in terms of timing and accuracy, as well as high reliability. 3. independent inputs, outputs and sample-and-hold controls allow user flexibility in system architecture. 4. low droop (0.01 m v/ m s) and internally compensated hold mode error results in superior system accuracy. 5. the AD684s fast settling time and low output impedance make it ideal for driving high speed analog to digital converters such as the ad578, ad674, ad7572 and the ad7672. 6. the AD684 is available in versions compliant with mil- std-883. refer to the analog devices military products databook or current AD684/883b data sheet for detailed specifications. product description the AD684 is a monolithic quad sample-and-hold amplifier (sha). it features four complete sampling channels, each controlled by an independent hold command. each sha is complete with an internal hold capacitor. the high accuracy sha channels are self-contained and require no external components or adjustments. the AD684 is manufactured on a bimos process which provides a merger of high performance bipolar circuitry and low power cmos logic. the AD684 is ideal for high performance, multichannel data acquisition systems. each sha channel can acquire a signal in less than 1 m s and retain the held value with a droop rate of less than 0.01 m v/ m s. excellent linearity and ac performance make the AD684 an ideal front end for high speed 12- and 14-bit adcs. the AD684 has a self-correcting architecture that minimizes hold mode errors and insures accuracy over temperature. each channel of the AD684 is capable of sourcing 5 ma and incorporates output short circuit protection. the AD684 is specified for three temperature ranges. the j grade device is specified for operation from 0 to +70 c, the a grade from C40 c to +85 c and the s grade from C55 c to +125 c. *protected by u.s. patent number 4,962,325.
AD684Cspecifications (t min to t max with v cc = +12 v 6 10%, v ee = C12 v 6 10%, unless otherwise noted) AD684j AD684a AD684s parameter min typ max min typ max min typ max units sampling characteristics acquisition time 10 v step to 0.01% 0.75 1.0 0.75 1.0 0.75 1.0 m s 10 v step to 0.1% 0.5 0.6 0.5 0.6 0.5 0.6 m s small signal bandwidth 4 4 4 mhz full power bandwidth 1 1 1 mhz hold characteristics effective aperture delay C35 C25 C15 C35 C25 C15 C35 C25 C15 ns aperture jitter 50 75 50 75 50 75 ps hold settling time (to 1 mv) 250 500 250 500 250 500 ns droop rate l 0.01 1 0.01 1 0.01 1 m v/ m s feedthrough (v in = 5 v, 100 khz) C90 C90 C90 db accuracy characteristics 1 hold mode offset C4 C1 +3 C4 1 +3 C4 C1 +3 mv hold mode offset drift 10 10 10 m v/ c sample mode offset 50 200 50 200 50 200 mv nonlinearity 0.002 0.003 0.002 0.003 0.003 0.005 % fs gain error 0.03 6 0.05 0.03 6 0.05 0.03 6 0.05 % fs interchannel characteristics interchannel isolation (v in = 5 v, 100 khz) 80 86 80 86 80 86 db interchannel aperture offset 150 300 150 300 150 300 ps interchannel offset 0.4 1.5 0.4 2.0 0.4 2.0 mv output characteristics output drive current 2 C5 +5 C5 +5 C5 +5 ma output resistance, dc 0.3 0.5 0.3 0.5 0.3 0.5 w total output noise (dc to 5 mhz) 150 150 150 m v rms sampled dc uncertainty 85 85 85 m v rms hold mode noise (dc to 5 mhz) 125 125 125 m v rms short circuit current 3 source 20 20 20 ma sink 10 10 10 ma input characteristics input voltage range C5 +5 C5 +5 C5 +5 v bias current 4 100 250 100 250 100 250 na 400 500 500 na input impedance 50 50 50 m w input capacitance 2 2 2 pf digital characteristics input voltage low 0.8 0.8 0.8 v input voltage high 2.0 2.0 2.0 v input current (v in = 5 v) 2 10 2 10 2 10 m a power supply characteristics operating voltage range (v cc , v ee ) 10.8 12 13.2 10.8 12 13.2 10.8 12 13.2 v supply current 18 25 18 25 18 26 ma +psrr 65 70 65 70 65 70 db Cpsrr 60 65 60 65 60 65 db power consumption 430 600 430 600 430 625 mw temperature range specified performance 0 +70 C40 +85 C55 +125 c package options 16-pin cerdip (q) AD684jq AD684aq AD684sq notes 1 specified and tested over an input range of 5 v. 2 maximum current the AD684 can source (or sink). testing guarantees that the accuracy of the held signal remains within 2.5 mv of its initial value. 3 the output is protected for a short circuit to common, v cc and v ee . 4 v cc and v ee at nominal voltage levels. specifications shown in boldface are tested on all production units at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. specifications subject to change without notice. rev. a C2C
AD684 rev. a C3C absolute maximum ratings* with spec respect to min max unit v cc common C0.3 +15 v v ee common C15 +0.3 v control inputs common C0.5 +7 v analog inputs common C12 +12 v output short circuit to ground, v cc or v ee indefinite max junction temperature +175 c storage C65 +150 c lead temperature (10 sec max) +300 c power dissipation 640 mw *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. pin configuration warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD684 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. ordering guide package model 1 temperature range option 2 AD684jq 0 to +70 c q-16 AD684aq C40 c to +85 c q-16 AD684sq C55 c to +125 c q-16 notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to the analog devices military prod- ucts databook or current AD684/883b data sheet. 2 q = cerdip.
AD684Ctypical characteristics rev. a C4C droop rate vs. temperature, v in = 0 v effective aperture delay vs. frequency bias current vs. input voltage supply current vs. temperature supply current vs. supply voltage interchannel isolation vs. frequency power supply rejection ratio vs. frequency acquisition time (to 0.01 %) vs. input step size
AD684 rev. a C5C definitions of specifications acquisition time the length of time that the sha must remain in the sample mode in order to acquire a full-scale input step to a given level of accuracy. small signal bandwidth the frequency at which the held output amplitude is 3 db below the input amplitude, under an input condition of a 100 mv p-p sine wave. full power bandwidth the frequency at which the held output amplitude is 3 db below the input amplitude, under an input condition of a 10 v p-p sine wave. effective aperture delay the difference between the switch delay and the analog delay of the sha channel. a negative number indicates that the analog portion of the overall delay is greater than the switch portion. this effective delay represents the point in time, relative to the hold command, that the input signal will be sampled. aperture jitter the variations in aperture delay for successive samples. aperture jitter puts an upper limit on the maximum frequency that can be accurately sampled. hold settling time the time required for the output to settle to within a specified level of accuracy of its final held value after the hold command has been given. droop rate the drift in output voltage while in the hold mode. feedthrough the attenuated version of a changing input signal that appears at the output when the sha is in the hold mode. hold mode offset the difference between the input signal and the held output. this offset term applies only in the hold mode and includes the error caused by charge injection and all other internal offsets. it is specified for an input of 0 v. tracking mode offset the difference between the input and output signals when the sha is in the track mode. nonlinearity the deviation from a straight line on a plot of input vs. (held) output as referenced to a straight line drawn between endpoints, over an input range of C5 v and +5 v. gain error deviation from a gain of +1 on the transfer function of input vs. held output. interchannel isolation the level of crosstalk between adjacent channels while in the sample (track) mode with a full scale 100 khz input signal. interchannel aperture offset the variation in aperture time between the four channels for a simultaneous hold command. differential offset the difference in hold mode offset between the four sha channels. power supply rejection ratio a measure of change in the held output voltage for a specified change in the positive or negative supply. sampled dc uncertainty the internal rms sha noise that is sampled onto the hold capacitor. hold mode noise the rms noise at the output of the sha while in the hold mode, specified over a given bandwidth. total output noise the total rms noise that is seen at the output of the sha while in the hold mode. it is the rms summation of the sampled dc uncertainty and the hold mode noise. output drive current the maximum current the sha can source (or sink) while maintaining a change in hold mode offset of less than 2.5 mv. functional description the AD684 is a complete quad sample-and-hold amplifier that provides high speed sampling to 12-bit accuracy in less than 1 m s. the AD684 is completely self-contained, including on-chip hold capacitors, and requires no external components or adjustments to perform the sampling function. each sha channel can operate independently, having its own input, output and sample/hold command. both inputs and outputs are treated as single ended signals, referred to common. the AD684 utilizes a proprietary circuit design which includes a self-correcting architecture. this sample-and-hold circuit corrects for internal errors after the hold command has been given, by compensating for amplifier gain and offset errors, and charge injection errors. due to the nature of the design, the sha output in the sample mode is not intended to provide an accurate representation of the input. however, in hold mode, the internal circuitry is reconfigured to produce an accurately held version of the input signal. to the right is a block diagram of the AD684. functional block diagram
AD684 rev. a C6C op484 dynamic performance the AD684 is compatible with 12-bit a-to-d converters in terms of both accuracy and speed. the fast acquisition time, fast hold settling time and good output drive capability allow the AD684 to be used with high speed, high resolution a-to-d converters like the ad674 and ad7672. the AD684s fast acquisition time provides high throughput rates for multichannel data acquisition systems. typically, the sample and hold can acquire a 10 v step in less than 750 ns. figure 1 shows the settling accuracy as a function of acquisition time. figure 1. v out settling vs. acquisition time the hold settling determines the required time, after the hold command is given, for the output to settle to its final specified accuracy. the typical settling behavior of the AD684 is shown in figure 2. the settling time of the AD684 is sufficiently fast to allow the sha, in most cases, to directly drive an a-to-d converter without the need for an added start convert delay. figure 2. typical AD684 hold mode hold mode offset the dc accuracy of the AD684 is determined primarily by the hold mode offset. the hold mode offset refers to the difference between the final held output voltage and the input signal at the time the hold command is given. the hold mode offset arises from a voltage error introduced onto the hold capacitor by charge injec- tion of the internal switches. the nominal hold mode offset is specified for a 0 v input condition. over the input range of C5 v to +5 v, the AD684 is also characterized for an effective gain error and nonlinearity of the held value, as shown in figure 3. as indicated by the AD684 specifications, the hold mode offset is very well matched between channels and stable over temperature. figure 3. hold mode offset, gain error and nonlinearity for applications where it is important to obtain zero offset, the hold mode offset may be nulled externally at the input to the a-to-d converter. adjustment of the offset may be accom- plished through the a-to-d itself or by an external amplifier with offset nulling capability (e.g., ad711). only a single adjustment of the offset is necessary for the four sha channels as a result of the excellent matching among them. the offset will change less than 0.5 mv over the specified temperature range. supply decoupling and grounding considerations as with any high speed, high resolution data acquisition system, the power supplies should be well regulated and free from excessive high frequency noise (ripple). the supply connection to the AD684 should also be capable of delivering transient currents to the device. to achieve the specified accuracy and dynamic performance, decoupling capacitors must be placed direc tly at both the positive and negative supply pins to common. ceramic type 0.1 m f capacitors should be connected from v cc and v ee to common. figure 4. basic grounding and decoupling diagram
AD684 rev. a C7C the AD684 does not provide separate analog and digital ground leads as is the case with most a-to-d converters. the common pin is the single ground terminal for the device. it is the refer- ence point for the sampled input voltage and the held output voltage and also the digital ground return path. the common pin should be connected to the reference (analog) ground of the a-to-d converter with a separate ground lead. since the analog and digital grounds in the 684 are connected internally, the common pin should also be connected to the digital ground, which is usually tied to analog common at the a-to-d converter. figure 4 illustrates the recommended decoupling and grounding practice. noise characteristics designers of data conversion circuits must also consider the effect of noise sources on the accuracy for the data acquisition system. a sample-and-hold amplifier that precedes the a-to-d converter introduces some noise and represents another source of uncertainty in the conversion process. the noise from the AD684 is specified as the total output noise, which includes both the sampled wideband noise of the sha in addition to the band limited output noise. the total output noise is the rms sum of the sampled dc uncertainty and the hold mode noise. a plot of the total output noise vs. the equivalent input bandwidth of the converter being used is given in figure 5. figure 5. rms noise vs. input bandwidth of adc driving the analog inputs for best performance, it is important to drive the AD684 analog inputs from a low impedance signal source. this enhances the sampling accuracy by minimizing the analog and digital crosstalk. signals which come from higher impedance sources (e.g., over 5k ohms) will have a relatively higher level of crosstalk. for applications where signals have high source impedance, an operational amplifier buffer in front of the AD684 is required. the ad713 (precision quad bifet op amp) is recommended for these applications. high frequency sampling aperture jitter and distortion are the primary factors which limit frequency domain performance of a sample-and-hold amplifier. aperture jitter modulates the phase of the hold command and produces an effective noise on the sampled analog input. the magnitude of the jitter induced noise is directly related to the frequency of the input signal. a graph showing the magnitude of the jitter induced error vs. frequency of the input signal is given in figure 6. the accuracy in sampling high frequency signals is also con- strained by the distortion and noise created by the sample-and- hold. the level of distortion increases with frequency and reduces the effective number of bits of the conversion. measurements of figures 7 and 8 were made using a 14-bit a-to-d converter with v in = 10 v p-p and a sample frequency of 100 ksps. figure 6. error magnitude vs. frequency figure 7. total harmonic distortion vs. frequency figure 8. signal/(noise and distortion) vs. frequency
AD684 rev. a C8C c1239aC10C8/91 printed in u.s.a. data acquisition applications figure 9 shows a typical data acquisition circuit using the AD684 and the high speed 12-bit a-to-d converter, the ad7672. four input signals are simultaneously sampled by the AD684 as the hold command is given. one of the four held outputs is selected by the adg201, quad cmos switch, and buffered by the ad711. the ad588 provides the reference voltage with switches a-b and c-d selecting a C5 v to +5 v or 0 to +5 v input range. figure 9. data acquisition system using the AD684 and the ad7672 outline dimensions dimensions shown in inches and (mm). q-16 16-lead cerdip
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